Tool: mp_target
Overview
Microprobe Target definition query tool. It provides an interface to dump different aspects of the target definition such as:
instruction information (input/ouput operands)
instruction format
instruction properties
microarchitecture component hierarchy
cache hierarchy details and properties
…
Basic usage
> mp_target -T TARGET
where:
Flag/Argument |
Description |
|---|---|
|
Target definition string. Check: Command line target definition scheme. |
Full usage
mp_target.py: INFO: Processing input arguments...
usage: mp_target.py [-h] [-P SEARCH_PATH [SEARCH_PATH ...]] [-V] [-v] [-d]
[-c CONFIG_FILE [CONFIG_FILE ...]] [-C FORCE_CONFIG_FILE]
[--dump-configuration-file OUTPUT_CONFIG_FILE]
[--dump-full-configuration-file OUTPUT_CONFIG_FILE]
[-A ARCHITECTURE_PATHS] [-M MICROARCHITECTURE_PATHS]
[-E ENVIRONMENT_PATHS] -T TARGET [--list-architectures]
[--list-microarchitectures] [--list-environments]
[--traceback] [--profile PROFILE_OUTPUT]
[-ins INSTRUCTIONS]
Microprobe Target definition query tool
optional arguments:
-h, --help show this help message and exit
-P SEARCH_PATH [SEARCH_PATH ...], --default_paths SEARCH_PATH [SEARCH_PATH ...]
Default search paths for microprobe target definitions
-V, --version Show Microprobe version and exit
-v, --verbosity Verbosity level (Values: [0,1,2,3,4]). Each time this
argument is specified the verbosity level is
increased. By default, no logging messages are shown.
These are the four levels available:
-v (1): critical messages
-v -v (2): critical and error messages
-v -v -v (3): critical, error and warning messages
-v -v -v -v (4): critical, error, warning and info messages
Specifying more than four verbosity flags, will
default to the maximum of four. If you need extra
information, enable the debug mode (--debug or -d
flags).
-d, --debug Enable debug mode in Microprobe framework. Lots of
output messages will be generated
Configuration arguments:
Command arguments related to configuration file handling
-c CONFIG_FILE [CONFIG_FILE ...], --configuration CONFIG_FILE [CONFIG_FILE ...]
Configuration file. The configuration files will be
readed in order of appearance. Values are reset by the
last configuration file in case of non-list values.
List values will be appended (not reset)
-C FORCE_CONFIG_FILE, --force-configuration FORCE_CONFIG_FILE
Force configuration file. Use this configuration file
as the default start configuration. This disables any
system-wide, or user-provided configuration.
--dump-configuration-file OUTPUT_CONFIG_FILE
Dump a configuration file with the actual
configuration used
--dump-full-configuration-file OUTPUT_CONFIG_FILE
Dump a configuration file with the actual
configuration used plus all the configuration options
not set
Target path arguments:
Command arguments related to target paths
-A ARCHITECTURE_PATHS, --architecture-paths ARCHITECTURE_PATHS
Search path for architecture definitions. Microprobe
will search in these paths for architecture
definitions
-M MICROARCHITECTURE_PATHS, --microarchitecture-paths MICROARCHITECTURE_PATHS
Search path for microarchitecture definitions.
Microprobe will search in these paths for
microarchitecture definitions
-E ENVIRONMENT_PATHS, --environment-paths ENVIRONMENT_PATHS
Search path for environment definitions. Microprobe
will search in these paths for environment definitions
Target arguments:
Command arguments related to target specification and queries
-T TARGET, --target TARGET
Target tuple. Microprobe follows a GCC-like target
definition scheme, where a target is defined by a
tuple as following:
<arch-name>-<uarch-name>-<env-name>
where:
<arch-name>: is the name of the architecture
<uarch-name>: is the name of the microarchitecture
<env-name>: is the name of the environment
One can use --list-* options to get the list of
definitions available in the default search paths or
the paths specified by the different --*-paths options
--list-architectures Generate a list of architectures available in the
defined search paths and exit
--list-microarchitectures
Generate a list of microarchitectures available in the
defined search paths and exit
--list-environments Generate a list of environments available in the
defined search paths and exit
Debug arguments:
Command arguments related to debugging facilities
--traceback show a traceback and starts a python debugger (pdb)
when an error occurs. 'pdb' is an interactive python
shell that facilitates the debugging of errors
--profile PROFILE_OUTPUT
dump profiling information into given file (see
'pstats' module)
Instruction:
Command arguments related to instruction information
-ins INSTRUCTIONS, --instructions INSTRUCTIONS
Comma separated list of instructions to obtain
information
Environment variables:
MICROPROBETEMPLATES Default path for microprobe templates
MICROPROBEDEBUG If set, enable debug
MICROPROBEDEBUGPASSES If set, enable debug during passes
MICROPROBEASMHEXFMT Assembly hexadecimal format. Options:
'all' -> All immediates in hex format
'address' -> Address immediates in hex format (default)
'none' -> All immediate in integer format
Example outputs
Example 1:
Command:
> mp_target -T riscv_v22-riscv_generic-riscv64_linux_gcc
Output:
mp_target.py: INFO: Processing input arguments...
mp_target.py: INFO: Arguments processed!
mp_target.py: INFO: Importing target definition...
mp_target.py: INFO: Dumping target riscv_v22-riscv_generic-riscv64_linux_gcc
--------------------------------------------------------------------------------
ISA Name: riscv_v22
ISA Description: riscv_v22
--------------------------------------------------------------------------------
Register Types:
freg: Floating Point Register 64 bits (bit size: 64)
SPR: Special Purpose Register (64 bits) (bit size: 64)
ireg: General Purpose Register 64 bits (bit size: 64)
--------------------------------------------------------------------------------
Architected registers:
F0 : Floating Point Register 0 (Type: freg)
F1 : Floating Point Register 1 (Type: freg)
F2 : Floating Point Register 2 (Type: freg)
F3 : Floating Point Register 3 (Type: freg)
F4 : Floating Point Register 4 (Type: freg)
F5 : Floating Point Register 5 (Type: freg)
F6 : Floating Point Register 6 (Type: freg)
F7 : Floating Point Register 7 (Type: freg)
F8 : Floating Point Register 8 (Type: freg)
F9 : Floating Point Register 9 (Type: freg)
F10 : Floating Point Register 10 (Type: freg)
F11 : Floating Point Register 11 (Type: freg)
F12 : Floating Point Register 12 (Type: freg)
F13 : Floating Point Register 13 (Type: freg)
F14 : Floating Point Register 14 (Type: freg)
F15 : Floating Point Register 15 (Type: freg)
F16 : Floating Point Register 16 (Type: freg)
F17 : Floating Point Register 17 (Type: freg)
F18 : Floating Point Register 18 (Type: freg)
F19 : Floating Point Register 19 (Type: freg)
F20 : Floating Point Register 20 (Type: freg)
F21 : Floating Point Register 21 (Type: freg)
F22 : Floating Point Register 22 (Type: freg)
F23 : Floating Point Register 23 (Type: freg)
F24 : Floating Point Register 24 (Type: freg)
F25 : Floating Point Register 25 (Type: freg)
F26 : Floating Point Register 26 (Type: freg)
F27 : Floating Point Register 27 (Type: freg)
F28 : Floating Point Register 28 (Type: freg)
F29 : Floating Point Register 29 (Type: freg)
F30 : Floating Point Register 30 (Type: freg)
F31 : Floating Point Register 31 (Type: freg)
PC : Program Counter register (Type: SPR)
X0 : General Purpose Register 0 (Type: ireg)
X1 : General Purpose Register 1 (Type: ireg)
X2 : General Purpose Register 2 (Type: ireg)
X3 : General Purpose Register 3 (Type: ireg)
X4 : General Purpose Register 4 (Type: ireg)
X5 : General Purpose Register 5 (Type: ireg)
X6 : General Purpose Register 6 (Type: ireg)
X7 : General Purpose Register 7 (Type: ireg)
X8 : General Purpose Register 8 (Type: ireg)
X9 : General Purpose Register 9 (Type: ireg)
X10 : General Purpose Register 10 (Type: ireg)
X11 : General Purpose Register 11 (Type: ireg)
X12 : General Purpose Register 12 (Type: ireg)
X13 : General Purpose Register 13 (Type: ireg)
X14 : General Purpose Register 14 (Type: ireg)
X15 : General Purpose Register 15 (Type: ireg)
X16 : General Purpose Register 16 (Type: ireg)
X17 : General Purpose Register 17 (Type: ireg)
X18 : General Purpose Register 18 (Type: ireg)
X19 : General Purpose Register 19 (Type: ireg)
X20 : General Purpose Register 20 (Type: ireg)
X21 : General Purpose Register 21 (Type: ireg)
X22 : General Purpose Register 22 (Type: ireg)
X23 : General Purpose Register 23 (Type: ireg)
X24 : General Purpose Register 24 (Type: ireg)
X25 : General Purpose Register 25 (Type: ireg)
X26 : General Purpose Register 26 (Type: ireg)
X27 : General Purpose Register 27 (Type: ireg)
X28 : General Purpose Register 28 (Type: ireg)
X29 : General Purpose Register 29 (Type: ireg)
X30 : General Purpose Register 30 (Type: ireg)
X31 : General Purpose Register 31 (Type: ireg)
--------------------------------------------------------------------------------
Instructions:
ADD ( ADD_V0) OPC:0x 33 Format: r Description: Add: Add rs2 to rs1 and place the result into rd
Definition
----------
Name : ADD_V0
Mnemonic : ADD
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
ADDI ( ADDI_V0) OPC:0x 13 Format: i Description: Add Immediate: Add sign-extended 12-bit immediate to register rs1 and place the result in rd
Definition
----------
Name : ADDI_V0
Mnemonic : ADDI
Opcode : 13
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_imm12
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : [['None', 1, 4611686018427387903], ['None', -1, 0]] (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
ADDIW ( ADDIW_V0) OPC:0x 1b Format: i Description: Add Immediate Word: Add sign-extended 12-bit immediate to register rs1 and place 32-bit sign extended result in rs2 zeroing upper bits
Definition
----------
Name : ADDIW_V0
Mnemonic : ADDIW
Opcode : 1b
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_imm12
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
ADDW ( ADDW_V0) OPC:0x 3b Format: r Description: Add Word: Add 32-bit value in rs2 to rs1 and place the 32-bit result into rd
Definition
----------
Name : ADDW_V0
Mnemonic : ADDW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOADD.D (AMOADD.D_V0) OPC:0x 2f Format: r-a Description: Atomic Add Double Word: Load double word from address in rs1 into rd, add rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOADD.D_V0
Mnemonic : AMOADD.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOADD.W (AMOADD.W_V0) OPC:0x 2f Format: r-a Description: Atomic Add Word: Load word from address in rs1 into rd, add rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOADD.W_V0
Mnemonic : AMOADD.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOAND.D (AMOAND.D_V0) OPC:0x 2f Format: r-a Description: Atomic And Double Word: Load double word from address in rs1 into rd, and rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOAND.D_V0
Mnemonic : AMOAND.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOAND.W (AMOAND.W_V0) OPC:0x 2f Format: r-a Description: Atomic And Word: Load word from address in rs1 into rd, and rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOAND.W_V0
Mnemonic : AMOAND.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMAX.D (AMOMAX.D_V0) OPC:0x 2f Format: r-a Description: Atomic Maximum Double Word: Load double word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (signed)
Definition
----------
Name : AMOMAX.D_V0
Mnemonic : AMOMAX.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMAX.W (AMOMAX.W_V0) OPC:0x 2f Format: r-a Description: Atomic Maximum Word: Load word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (signed)
Definition
----------
Name : AMOMAX.W_V0
Mnemonic : AMOMAX.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMAXU.D (AMOMAXU.D_V0) OPC:0x 2f Format: r-a Description: Atomic Maximum Unsigned Double Word: Load double word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (unsigned)
Definition
----------
Name : AMOMAXU.D_V0
Mnemonic : AMOMAXU.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMAXU.W (AMOMAXU.W_V0) OPC:0x 2f Format: r-a Description: Atomic Maximum Unsigned Word: Load word from address in rs1 into rd, find maximum of rd and rs2, write the result to the address in rs1 (unsigned)
Definition
----------
Name : AMOMAXU.W_V0
Mnemonic : AMOMAXU.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMIN.D (AMOMIN.D_V0) OPC:0x 2f Format: r-a Description: Atomic Minimum Double Word: Load double word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (signed)
Definition
----------
Name : AMOMIN.D_V0
Mnemonic : AMOMIN.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMIN.W (AMOMIN.W_V0) OPC:0x 2f Format: r-a Description: Atomic Minimum Word: Load word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (signed)
Definition
----------
Name : AMOMIN.W_V0
Mnemonic : AMOMIN.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMINU.D (AMOMINU.D_V0) OPC:0x 2f Format: r-a Description: Atomic Minimum Unsigned Double Word: Load double word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (unsigned)
Definition
----------
Name : AMOMINU.D_V0
Mnemonic : AMOMINU.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOMINU.W (AMOMINU.W_V0) OPC:0x 2f Format: r-a Description: Atomic Minimum Unsigned Word: Load word from address in rs1 into rd, find minimum of rd and rs2, write the result to the address in rs1 (unsigned)
Definition
----------
Name : AMOMINU.W_V0
Mnemonic : AMOMINU.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOOR.D (AMOOR.D_V0) OPC:0x 2f Format: r-a Description: Atomic Or Double Word: Load double word from address in rs1 into rd, or rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOOR.D_V0
Mnemonic : AMOOR.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOOR.W (AMOOR.W_V0) OPC:0x 2f Format: r-a Description: Atomic Or Word: Load word from address in rs1 into rd, or rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOOR.W_V0
Mnemonic : AMOOR.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOSWAP.D (AMOSWAP.D_V0) OPC:0x 2f Format: r-a Description: Atomic Swap Double Word: Load double word from address in rs1 into rd, swap rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOSWAP.D_V0
Mnemonic : AMOSWAP.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOSWAP.W (AMOSWAP.W_V0) OPC:0x 2f Format: r-a Description: Atomic Swap Word: Load word from address in rs1 into rd, swap rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOSWAP.W_V0
Mnemonic : AMOSWAP.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOXOR.D (AMOXOR.D_V0) OPC:0x 2f Format: r-a Description: Atomic Xor Double Word: Load double word from address in rs1 into rd, xor rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOXOR.D_V0
Mnemonic : AMOXOR.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AMOXOR.W (AMOXOR.W_V0) OPC:0x 2f Format: r-a Description: Atomic Xor Word: Load word from address in rs1 into rd, xor rd and rs2, write the result to the address in rs1
Definition
----------
Name : AMOXOR.W_V0
Mnemonic : AMOXOR.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AND ( AND_V0) OPC:0x 33 Format: r Description: And: Set rd to the bitwise and of rs1 and rs2
Definition
----------
Name : AND_V0
Mnemonic : AND
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
ANDI ( ANDI_V0) OPC:0x 13 Format: i Description: And Immediate: Set rd to the bitwise and of rs1 with the sign-extended 12-bit immediate
Definition
----------
Name : ANDI_V0
Mnemonic : ANDI
Opcode : 13
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_imm12
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
AUIPC ( AUIPC_V0) OPC:0x 17 Format: u+o Description: Add Upper Immediate to PC: Place the PC plus the 20-bit signed immediate (shited 12 bits left) into rd (used before JALR)
Definition
----------
Name : AUIPC_V0
Mnemonic : AUIPC
Opcode : 17
Operand u_imm20 : u.imm20 : 20-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
u+o : No description ([ u_imm20 | rd |opcode ])
Assembly : OPC rd, u_imm20
Fieldname : u_imm20 (bitsize: 20)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
BEQ ( BEQ_V0) OPC:0x 63 Format: sb Description: Branch Equal: Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 == rs2
Definition
----------
Name : BEQ_V0
Mnemonic : BEQ
Opcode : 63
Operand sb_imm7 : @sb_imm7 : Relative displacement (bit size 7) (InstructionAddressRelativeOperand) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand sb_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['sb_imm7']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
sb : No description ([sb_imm7| rs2 | rs1 |funct3|sb_imm5|opcode ])
Assembly : OPC rs1, rs2, sb_imm12
Fieldname : sb_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : sb_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
BGE ( BGE_V0) OPC:0x 63 Format: sb Description: Branch Greater than Equal: Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 >= rs2 (signed)
Definition
----------
Name : BGE_V0
Mnemonic : BGE
Opcode : 63
Operand sb_imm7 : @sb_imm7 : Relative displacement (bit size 7) (InstructionAddressRelativeOperand) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand sb_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['sb_imm7']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
sb : No description ([sb_imm7| rs2 | rs1 |funct3|sb_imm5|opcode ])
Assembly : OPC rs1, rs2, sb_imm12
Fieldname : sb_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : sb_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
BGEU ( BGEU_V0) OPC:0x 63 Format: sb Description: Branch Greater than Equal Unsigned: Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 >= rs2 (unsigned)
Definition
----------
Name : BGEU_V0
Mnemonic : BGEU
Opcode : 63
Operand sb_imm7 : @sb_imm7 : Relative displacement (bit size 7) (InstructionAddressRelativeOperand) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand sb_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['sb_imm7']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
sb : No description ([sb_imm7| rs2 | rs1 |funct3|sb_imm5|opcode ])
Assembly : OPC rs1, rs2, sb_imm12
Fieldname : sb_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : sb_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
BLT ( BLT_V0) OPC:0x 63 Format: sb Description: Branch Less Than: Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 < rs2 (signed)
Definition
----------
Name : BLT_V0
Mnemonic : BLT
Opcode : 63
Operand sb_imm7 : @sb_imm7 : Relative displacement (bit size 7) (InstructionAddressRelativeOperand) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand sb_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['sb_imm7']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
sb : No description ([sb_imm7| rs2 | rs1 |funct3|sb_imm5|opcode ])
Assembly : OPC rs1, rs2, sb_imm12
Fieldname : sb_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : sb_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
BLTU ( BLTU_V0) OPC:0x 63 Format: sb Description: Branch Less Than Unsigned: Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 < rs2 (unsigned)
Definition
----------
Name : BLTU_V0
Mnemonic : BLTU
Opcode : 63
Operand sb_imm7 : @sb_imm7 : Relative displacement (bit size 7) (InstructionAddressRelativeOperand) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand sb_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['sb_imm7']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
sb : No description ([sb_imm7| rs2 | rs1 |funct3|sb_imm5|opcode ])
Assembly : OPC rs1, rs2, sb_imm12
Fieldname : sb_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : sb_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
BNE ( BNE_V0) OPC:0x 63 Format: sb Description: Branch Not Equal: Branch to PC relative 12-bit signed immediate (shifted 1 bit left) if rs1 != rs2
Definition
----------
Name : BNE_V0
Mnemonic : BNE
Opcode : 63
Operand sb_imm7 : @sb_imm7 : Relative displacement (bit size 7) (InstructionAddressRelativeOperand) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand sb_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['sb_imm7']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
sb : No description ([sb_imm7| rs2 | rs1 |funct3|sb_imm5|opcode ])
Assembly : OPC rs1, rs2, sb_imm12
Fieldname : sb_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : sb_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.ADD ( C.ADD_V0) OPC:0x 2 Format: cr Description: No description
Definition
----------
Name : C.ADD_V0
Mnemonic : C.ADD
Opcode : 2
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Operand rs2 : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Instr. Checks :
Target Checks :
Format
------
cr : No description ([funct4| rd | rs2 |opcode_compressed])
Assembly : OPC rd, rs2
Fieldname : funct4 (bitsize: 4)
Fieldname : rd (bitsize: 5)
Fieldname : rs2 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.ADDI4SPN (C.ADDI4SPN_V0) OPC:0x 0 Format: ciw Description: Add azero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and write the result to rd'
Definition
----------
Name : C.ADDI4SPN_V0
Mnemonic : C.ADDI4SPN
Opcode : 0
Operand cs_imm8 : nz_imm8 : Non-zero 8-bit immediate (OperandImmRange) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
ciw : No description ([funct3| cs_imm8 |crd|opcode_compressed])
Assembly : OPC crd, sp, cs_imm8
Fieldname : funct3 (bitsize: 3)
Fieldname : cs_imm8 (bitsize: 8)
Fieldname : crd (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.ADDI16SP (C.ADDI16SP_V0) OPC:0x 1 Format: ci_s Description: No description
Definition
----------
Name : C.ADDI16SP_V0
Mnemonic : C.ADDI16SP
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : spreg : No description (OperandReg) -- Input: True Output: True
Operand cs_imm5 : nz_imm10 : Non-zero 10-bit immediate (OperandImmRange) -- Input: True Output: False
Implicit Operand : X2 : The X2 Integer Register (Stack Pointer) (OperandConstReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
ci_s : No description ([funct3|c_imm1| rd |cs_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : cs_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.ADDI ( C.ADDI_V0) OPC:0x 1 Format: ci_i Description: No description
Definition
----------
Name : C.ADDI_V0
Mnemonic : C.ADDI
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Operand ci_imm5 : simm6 : 6-bit immediate (signed) (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_i : No description ([funct3|c_imm1| rd |ci_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : ci_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.ADDIW (C.ADDIW_V0) OPC:0x 1 Format: ci_i Description: No description
Definition
----------
Name : C.ADDIW_V0
Mnemonic : C.ADDIW
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Operand ci_imm5 : simm6 : 6-bit immediate (signed) (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_i : No description ([funct3|c_imm1| rd |ci_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : ci_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.ADDW ( C.ADDW_V0) OPC:0x 1 Format: ca Description: No description
Definition
----------
Name : C.ADDW_V0
Mnemonic : C.ADDW
Opcode : 1
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand crs2 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ca : No description ([funct6|crd|funct2|crs2|opcode_compressed])
Assembly : OPC crd, crs2
Fieldname : funct6 (bitsize: 6)
Fieldname : crd (bitsize: 3)
Fieldname : funct2 (bitsize: 2)
Fieldname : crs2 (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.AND ( C.AND_V0) OPC:0x 1 Format: ca Description: No description
Definition
----------
Name : C.AND_V0
Mnemonic : C.AND
Opcode : 1
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand crs2 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ca : No description ([funct6|crd|funct2|crs2|opcode_compressed])
Assembly : OPC crd, crs2
Fieldname : funct6 (bitsize: 6)
Fieldname : crd (bitsize: 3)
Fieldname : funct2 (bitsize: 2)
Fieldname : crs2 (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.ANDI ( C.ANDI_V0) OPC:0x 1 Format: cb_s Description: No description
Definition
----------
Name : C.ANDI_V0
Mnemonic : C.ANDI
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand ci_imm5 : simm6 : 6-bit immediate (signed) (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
cb_s : No description ([funct3|c_imm1|funct2|crd|ci_imm5|opcode_compressed])
Assembly : OPC crd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : funct2 (bitsize: 2)
Fieldname : crd (bitsize: 3)
Fieldname : ci_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.BEQZ ( C.BEQZ_V0) OPC:0x 1 Format: cb_b Description: No description
Definition
----------
Name : C.BEQZ_V0
Mnemonic : C.BEQZ
Opcode : 1
Operand c_imm3 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crs1 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand cb_imm5 : sbimm9 : 9-bit signed immediate (InstructionAddressRelativeOperand) -- Input: True Output: False
Memory Operand 0 :
Address : ['cb_imm5']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
cb_b : No description ([funct3|c_imm3|crs1|cb_imm5|opcode_compressed])
Assembly : OPC crs1, c_imm8
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : cb_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.BNEZ ( C.BNEZ_V0) OPC:0x 1 Format: cb_b Description: No description
Definition
----------
Name : C.BNEZ_V0
Mnemonic : C.BNEZ
Opcode : 1
Operand c_imm3 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crs1 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand cb_imm5 : sbimm9 : 9-bit signed immediate (InstructionAddressRelativeOperand) -- Input: True Output: False
Memory Operand 0 :
Address : ['cb_imm5']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
cb_b : No description ([funct3|c_imm3|crs1|cb_imm5|opcode_compressed])
Assembly : OPC crs1, c_imm8
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : cb_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : True (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.EBREAK (C.EBREAK_V0) OPC:0x 2 Format:c_funct14 Description: No description
Definition
----------
Name : C.EBREAK_V0
Mnemonic : C.EBREAK
Opcode : 2
Instr. Checks :
Target Checks :
Format
------
c_funct14 : No description ([funct4| funct10 |opcode_compressed])
Assembly : OPC
Fieldname : funct4 (bitsize: 4)
Fieldname : funct10 (bitsize: 10)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.FLD ( C.FLD_V0) OPC:0x 0 Format: cl_d+f Description: No description
Definition
----------
Name : C.FLD_V0
Mnemonic : C.FLD
Opcode : 0
Operand cd_imm3 : imm8_d : 8-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Operand crs1 : crega : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand c_imm2 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand fcrd : fcreg : Compressed Instruction Floating Point Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['cd_imm3', 'crs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
cl_d+f : No description ([funct3|cd_imm3|crs1|c_imm2|fcrd|opcode_compressed])
Assembly : OPC fcrd, c_imm5(crs1)
Fieldname : funct3 (bitsize: 3)
Fieldname : cd_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : c_imm2 (bitsize: 2)
Fieldname : fcrd (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.FLDSP (C.FLDSP_V0) OPC:0x 2 Format: ci_d+f Description: No description
Definition
----------
Name : C.FLDSP_V0
Mnemonic : C.FLDSP
Opcode : 2
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Operand cd_imm5 : imm9_d : 9-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Memory Operand 0 :
Address : ['X2', 'cd_imm5']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Implicit Operand : X2 : The X2 Integer Register (Stack Pointer) (OperandConstReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_d+f : No description ([funct3|c_imm1| frd |cd_imm5|opcode_compressed])
Assembly : OPC frd, c_imm6(sp)
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : frd (bitsize: 5)
Fieldname : cd_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.FSD ( C.FSD_V0) OPC:0x 0 Format: cl_d+f Description: No description
Definition
----------
Name : C.FSD_V0
Mnemonic : C.FSD
Opcode : 0
Operand cd_imm3 : imm8_d : 8-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Operand crs1 : crega : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand c_imm2 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand fcrd : fcreg : Compressed Instruction Floating Point Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['cd_imm3', 'crs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
cl_d+f : No description ([funct3|cd_imm3|crs1|c_imm2|fcrd|opcode_compressed])
Assembly : OPC fcrd, c_imm5(crs1)
Fieldname : funct3 (bitsize: 3)
Fieldname : cd_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : c_imm2 (bitsize: 2)
Fieldname : fcrd (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.FSDSP (C.FSDSP_V0) OPC:0x 2 Format: css_d+f Description: No description
Definition
----------
Name : C.FSDSP_V0
Mnemonic : C.FSDSP
Opcode : 2
Operand cd_imm6 : imm9_d : 9-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Memory Operand 0 :
Address : ['X2', 'cd_imm6']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Implicit Operand : X2 : The X2 Integer Register (Stack Pointer) (OperandConstReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
css_d+f : No description ([funct3|cd_imm6|frs2 |opcode_compressed])
Assembly : OPC frs2, cd_imm6(sp)
Fieldname : funct3 (bitsize: 3)
Fieldname : cd_imm6 (bitsize: 6)
Fieldname : frs2 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.J ( C.J_V0) OPC:0x 1 Format: cj Description: No description
Definition
----------
Name : C.J_V0
Mnemonic : C.J
Opcode : 1
Operand c_imm11 : imm11 : 11-bit immediate (InstructionAddressRelativeOperand) -- Input: True Output: False
Memory Operand 0 :
Address : ['c_imm11']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
cj : No description ([funct3| c_imm11 |opcode_compressed])
Assembly : OPC c_imm11
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm11 (bitsize: 11)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.JALR ( C.JALR_V0) OPC:0x 2 Format: cr_jr Description: No description
Definition
----------
Name : C.JALR_V0
Mnemonic : C.JALR
Opcode : 2
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Operand rs2_jr : X0 : The X0 Integer Register (Stack Pointer) (OperandReg) -- Input: True Output: False
Memory Operand 0 :
Address : ['rd']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Implicit Operand : X1 : The X1 Integer Register (Return Address) (OperandConstReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
cr_jr : No description ([funct4| rd |rs2_jr|opcode_compressed])
Assembly : OPC rd
Fieldname : funct4 (bitsize: 4)
Fieldname : rd (bitsize: 5)
Fieldname : rs2_jr (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.JR ( C.JR_V0) OPC:0x 2 Format: cr_jr Description: No description
Definition
----------
Name : C.JR_V0
Mnemonic : C.JR
Opcode : 2
Operand rd : nzreg_ab : Non-zero Integer Registers (address base) (OperandReg) -- Input: True Output: False
Operand rs2_jr : X0 : The X0 Integer Register (Stack Pointer) (OperandReg) -- Input: True Output: False
Memory Operand 0 :
Address : ['rd']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
cr_jr : No description ([funct4| rd |rs2_jr|opcode_compressed])
Assembly : OPC rd
Fieldname : funct4 (bitsize: 4)
Fieldname : rd (bitsize: 5)
Fieldname : rs2_jr (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.LD ( C.LD_V0) OPC:0x 0 Format: cl_d Description: No description
Definition
----------
Name : C.LD_V0
Mnemonic : C.LD
Opcode : 0
Operand cd_imm3 : imm8_d : 8-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Operand crs1 : crega : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand c_imm2 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['cd_imm3', 'crs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
cl_d : No description ([funct3|cd_imm3|crs1|c_imm2|crd|opcode_compressed])
Assembly : OPC crd, c_imm5(crs1)
Fieldname : funct3 (bitsize: 3)
Fieldname : cd_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : c_imm2 (bitsize: 2)
Fieldname : crd (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.LDSP ( C.LDSP_V0) OPC:0x 2 Format: ci_d Description: No description
Definition
----------
Name : C.LDSP_V0
Mnemonic : C.LDSP
Opcode : 2
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: False Output: True
Operand cd_imm5 : imm9_d : 9-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Memory Operand 0 :
Address : ['X2', 'cd_imm5']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Implicit Operand : X2 : The X2 Integer Register (Stack Pointer) (OperandConstReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_d : No description ([funct3|c_imm1| rd |cd_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6(sp)
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : cd_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.LI ( C.LI_V0) OPC:0x 1 Format: ci_i Description: No description
Definition
----------
Name : C.LI_V0
Mnemonic : C.LI
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Operand ci_imm5 : simm6 : 6-bit immediate (signed) (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_i : No description ([funct3|c_imm1| rd |ci_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : ci_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.LUI ( C.LUI_V0) OPC:0x 1 Format: ci_u Description: No description
Definition
----------
Name : C.LUI_V0
Mnemonic : C.LUI
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : nzspreg : Non-zero Non-stack-pointer Integer Registers (OperandReg) -- Input: True Output: True
Operand cu_imm5 : imm20_clui : No description (OperandValueSet) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_u : No description ([funct3|c_imm1| rd |cu_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : cu_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.LW ( C.LW_V0) OPC:0x 0 Format: cl_w Description: No description
Definition
----------
Name : C.LW_V0
Mnemonic : C.LW
Opcode : 0
Operand cw_imm3 : imm7_w : 7-bit immediate (Word Stepping) (OperandImmRange) -- Input: True Output: False
Operand crs1 : crega : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand c_imm2 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['cw_imm3', 'crs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
cl_w : No description ([funct3|cw_imm3|crs1|c_imm2|crd|opcode_compressed])
Assembly : OPC crd, c_imm5(crs1)
Fieldname : funct3 (bitsize: 3)
Fieldname : cw_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : c_imm2 (bitsize: 2)
Fieldname : crd (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.LWSP ( C.LWSP_V0) OPC:0x 2 Format: ci_w Description: No description
Definition
----------
Name : C.LWSP_V0
Mnemonic : C.LWSP
Opcode : 2
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: False Output: True
Operand cw_imm5 : imm8_w : 8-bit immediate (Word Stepping) (OperandImmRange) -- Input: True Output: False
Memory Operand 0 :
Address : ['X2', 'cw_imm5']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Implicit Operand : X2 : The X2 Integer Register (Stack Pointer) (OperandConstReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_w : No description ([funct3|c_imm1| rd |cw_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6(sp)
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : cw_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.MV ( C.MV_V0) OPC:0x 2 Format: cr Description: No description
Definition
----------
Name : C.MV_V0
Mnemonic : C.MV
Opcode : 2
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Operand rs2 : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Instr. Checks :
Target Checks :
Format
------
cr : No description ([funct4| rd | rs2 |opcode_compressed])
Assembly : OPC rd, rs2
Fieldname : funct4 (bitsize: 4)
Fieldname : rd (bitsize: 5)
Fieldname : rs2 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.NOP ( C.NOP_V0) OPC:0x 1 Format:c_funct14 Description: No description
Definition
----------
Name : C.NOP_V0
Mnemonic : C.NOP
Opcode : 1
Instr. Checks :
Target Checks :
Format
------
c_funct14 : No description ([funct4| funct10 |opcode_compressed])
Assembly : OPC
Fieldname : funct4 (bitsize: 4)
Fieldname : funct10 (bitsize: 10)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.OR ( C.OR_V0) OPC:0x 1 Format: ca Description: No description
Definition
----------
Name : C.OR_V0
Mnemonic : C.OR
Opcode : 1
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand crs2 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ca : No description ([funct6|crd|funct2|crs2|opcode_compressed])
Assembly : OPC crd, crs2
Fieldname : funct6 (bitsize: 6)
Fieldname : crd (bitsize: 3)
Fieldname : funct2 (bitsize: 2)
Fieldname : crs2 (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SD ( C.SD_V0) OPC:0x 0 Format: cl_d Description: No description
Definition
----------
Name : C.SD_V0
Mnemonic : C.SD
Opcode : 0
Operand cd_imm3 : imm8_d : 8-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Operand crs1 : crega : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand c_imm2 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['cd_imm3', 'crs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
cl_d : No description ([funct3|cd_imm3|crs1|c_imm2|crd|opcode_compressed])
Assembly : OPC crd, c_imm5(crs1)
Fieldname : funct3 (bitsize: 3)
Fieldname : cd_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : c_imm2 (bitsize: 2)
Fieldname : crd (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SDSP ( C.SDSP_V0) OPC:0x 2 Format: css_d Description: No description
Definition
----------
Name : C.SDSP_V0
Mnemonic : C.SDSP
Opcode : 2
Operand cd_imm6 : imm9_d : 9-bit immediate (Double Stepping) (OperandImmRange) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Memory Operand 0 :
Address : ['X2', 'cd_imm6']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Implicit Operand : X2 : The X2 Integer Register (Stack Pointer) (OperandConstReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
css_d : No description ([funct3|cd_imm6| rs2 |opcode_compressed])
Assembly : OPC rs2, cd_imm6(sp)
Fieldname : funct3 (bitsize: 3)
Fieldname : cd_imm6 (bitsize: 6)
Fieldname : rs2 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SLLI ( C.SLLI_V0) OPC:0x 2 Format: ci_ls Description: No description
Definition
----------
Name : C.SLLI_V0
Mnemonic : C.SLLI
Opcode : 2
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand rd : nzreg : Non-zero Integer Registers (OperandReg) -- Input: True Output: True
Operand cls_imm5 : nz_u.imm6 : Non-zero 6-bit immediate (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ci_ls : No description ([funct3|c_imm1| rd |cls_imm5|opcode_compressed])
Assembly : OPC rd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : rd (bitsize: 5)
Fieldname : cls_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SRAI ( C.SRAI_V0) OPC:0x 1 Format: cb_ls Description: No description
Definition
----------
Name : C.SRAI_V0
Mnemonic : C.SRAI
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand cls_imm5 : nz_u.imm6 : Non-zero 6-bit immediate (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
cb_ls : No description ([funct3|c_imm1|funct2|crd|cls_imm5|opcode_compressed])
Assembly : OPC crd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : funct2 (bitsize: 2)
Fieldname : crd (bitsize: 3)
Fieldname : cls_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SRLI ( C.SRLI_V0) OPC:0x 1 Format: cb_ls Description: No description
Definition
----------
Name : C.SRLI_V0
Mnemonic : C.SRLI
Opcode : 1
Operand c_imm1 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand cls_imm5 : nz_u.imm6 : Non-zero 6-bit immediate (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
cb_ls : No description ([funct3|c_imm1|funct2|crd|cls_imm5|opcode_compressed])
Assembly : OPC crd, c_imm6
Fieldname : funct3 (bitsize: 3)
Fieldname : c_imm1 (bitsize: 1)
Fieldname : funct2 (bitsize: 2)
Fieldname : crd (bitsize: 3)
Fieldname : cls_imm5 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SUB ( C.SUB_V0) OPC:0x 1 Format: ca Description: No description
Definition
----------
Name : C.SUB_V0
Mnemonic : C.SUB
Opcode : 1
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand crs2 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ca : No description ([funct6|crd|funct2|crs2|opcode_compressed])
Assembly : OPC crd, crs2
Fieldname : funct6 (bitsize: 6)
Fieldname : crd (bitsize: 3)
Fieldname : funct2 (bitsize: 2)
Fieldname : crs2 (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SUBW ( C.SUBW_V0) OPC:0x 1 Format: ca Description: No description
Definition
----------
Name : C.SUBW_V0
Mnemonic : C.SUBW
Opcode : 1
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand crs2 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ca : No description ([funct6|crd|funct2|crs2|opcode_compressed])
Assembly : OPC crd, crs2
Fieldname : funct6 (bitsize: 6)
Fieldname : crd (bitsize: 3)
Fieldname : funct2 (bitsize: 2)
Fieldname : crs2 (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SW ( C.SW_V0) OPC:0x 0 Format: cl_w Description: No description
Definition
----------
Name : C.SW_V0
Mnemonic : C.SW
Opcode : 0
Operand cw_imm3 : imm7_w : 7-bit immediate (Word Stepping) (OperandImmRange) -- Input: True Output: False
Operand crs1 : crega : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Operand c_imm2 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['cw_imm3', 'crs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
cl_w : No description ([funct3|cw_imm3|crs1|c_imm2|crd|opcode_compressed])
Assembly : OPC crd, c_imm5(crs1)
Fieldname : funct3 (bitsize: 3)
Fieldname : cw_imm3 (bitsize: 3)
Fieldname : crs1 (bitsize: 3)
Fieldname : c_imm2 (bitsize: 2)
Fieldname : crd (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.SWSP ( C.SWSP_V0) OPC:0x 2 Format: css_w Description: No description
Definition
----------
Name : C.SWSP_V0
Mnemonic : C.SWSP
Opcode : 2
Operand cw_imm6 : imm8_w : 8-bit immediate (Word Stepping) (OperandImmRange) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Memory Operand 0 :
Address : ['X2', 'cw_imm6']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Implicit Operand : X2 : The X2 Integer Register (Stack Pointer) (OperandConstReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
css_w : No description ([funct3|cw_imm6| rs2 |opcode_compressed])
Assembly : OPC rs2, cw_imm6(sp)
Fieldname : funct3 (bitsize: 3)
Fieldname : cw_imm6 (bitsize: 6)
Fieldname : rs2 (bitsize: 5)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
C.XOR ( C.XOR_V0) OPC:0x 1 Format: ca Description: No description
Definition
----------
Name : C.XOR_V0
Mnemonic : C.XOR
Opcode : 1
Operand crd : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: False Output: True
Operand crs2 : creg : Compressed Instruction Integer Registers (OperandReg) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
ca : No description ([funct6|crd|funct2|crs2|opcode_compressed])
Assembly : OPC crd, crs2
Fieldname : funct6 (bitsize: 6)
Fieldname : crd (bitsize: 3)
Fieldname : funct2 (bitsize: 2)
Fieldname : crs2 (bitsize: 3)
Fieldname : opcode_compressed (bitsize: 2)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
CSRRS ( CSRRS_V0) OPC:0x 73 Format: csr Description: No description
Definition
----------
Name : CSRRS_V0
Mnemonic : CSRRS
Opcode : 73
Operand u_imm12 : u.imm12 : unsigned 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
csr : No description ([ u_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, u_imm12, rs1
Fieldname : u_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
CSRRW ( CSRRW_V0) OPC:0x 73 Format: csr Description: No description
Definition
----------
Name : CSRRW_V0
Mnemonic : CSRRW
Opcode : 73
Operand u_imm12 : u.imm12 : unsigned 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
csr : No description ([ u_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, u_imm12, rs1
Fieldname : u_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
DIV ( DIV_V0) OPC:0x 33 Format: r Description: Divide Signed: Divide rs1 (dividend) by rs2 (divisor) and place the quotient in rd (signed)
Definition
----------
Name : DIV_V0
Mnemonic : DIV
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
DIVU ( DIVU_V0) OPC:0x 33 Format: r Description: Divide Unsigned: Divide rs1 (dividend) by rs2 (divisor) and place the quotient in rd (unsigned)
Definition
----------
Name : DIVU_V0
Mnemonic : DIVU
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
DIVUW ( DIVUW_V0) OPC:0x 3b Format: r Description: Divide Unsigned Word: Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the quotient in rd (unsigned)
Definition
----------
Name : DIVUW_V0
Mnemonic : DIVUW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
DIVW ( DIVW_V0) OPC:0x 3b Format: r Description: Divide Signed Word: Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the quotient in rd (signed)
Definition
----------
Name : DIVW_V0
Mnemonic : DIVW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
EBREAK ( EBREAK_V0) OPC:0x 73 Format: sys Description: No description
Definition
----------
Name : EBREAK_V0
Mnemonic : EBREAK
Opcode : 73
Instr. Checks :
Target Checks :
Format
------
sys : No description ([ funct25 |opcode ])
Assembly : OPC
Fieldname : funct25 (bitsize: 25)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
ECALL ( ECALL_V0) OPC:0x 73 Format: sys Description: No description
Definition
----------
Name : ECALL_V0
Mnemonic : ECALL
Opcode : 73
Instr. Checks :
Target Checks :
Format
------
sys : No description ([ funct25 |opcode ])
Assembly : OPC
Fieldname : funct25 (bitsize: 25)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FADD.D ( FADD.D_V0) OPC:0x 53 Format: r-m+3f Description: FP Add (DP): Add the double-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FADD.D_V0
Mnemonic : FADD.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FADD.D ( FADD.D_V1) OPC:0x 53 Format:r-m+3frm Description: FP Add (DP): Add the double-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FADD.D_V1
Mnemonic : FADD.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FADD.S ( FADD.S_V0) OPC:0x 53 Format: r-m+3f Description: FP Add (SP): Add the single-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FADD.S_V0
Mnemonic : FADD.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FADD.S ( FADD.S_V1) OPC:0x 53 Format:r-m+3frm Description: FP Add (SP): Add the single-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FADD.S_V1
Mnemonic : FADD.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCLASS.D (FCLASS.D_V0) OPC:0x 53 Format: r+rf2 Description: FP Classify (DP): Set rd to a 10-bit mask indicating the class of the double-precision value in frs1
Definition
----------
Name : FCLASS.D_V0
Mnemonic : FCLASS.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rf2 : No description ([funct5|funct2|rs2c |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCLASS.S (FCLASS.S_V0) OPC:0x 53 Format: r+rf2 Description: FP Classify (SP): Set rd to a 10-bit mask indicating the class of the single-precision value in frs1
Definition
----------
Name : FCLASS.S_V0
Mnemonic : FCLASS.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rf2 : No description ([funct5|funct2|rs2c |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.D.L (FCVT.D.L_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Double Word to Float (DP): Convert the 64-bit signed integer in rs1 to a double-precision value, then write the result to frd
Definition
----------
Name : FCVT.D.L_V0
Mnemonic : FCVT.D.L
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.D.L (FCVT.D.L_V1) OPC:0x 53 Format:r-m+fr2rm Description: FP Convert Double Word to Float (DP): Convert the 64-bit signed integer in rs1 to a double-precision value, then write the result to frd
Definition
----------
Name : FCVT.D.L_V1
Mnemonic : FCVT.D.L
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2rm : No description ([funct5|funct2|rs2c | rs1 |rm| frd |opcode ])
Assembly : OPC frd, rs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.D.LU (FCVT.D.LU_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Double Word Unsigned Float (DP): Convert the 64-bit unsigned integer in rs1 to a double-precision value, then write the result to frd
Definition
----------
Name : FCVT.D.LU_V0
Mnemonic : FCVT.D.LU
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.D.LU (FCVT.D.LU_V1) OPC:0x 53 Format:r-m+fr2rm Description: FP Convert Double Word Unsigned Float (DP): Convert the 64-bit unsigned integer in rs1 to a double-precision value, then write the result to frd
Definition
----------
Name : FCVT.D.LU_V1
Mnemonic : FCVT.D.LU
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2rm : No description ([funct5|funct2|rs2c | rs1 |rm| frd |opcode ])
Assembly : OPC frd, rs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.D.S (FCVT.D.S_V0) OPC:0x 53 Format: r-m+ff2 Description: FP Convert SP to DP: Convert the single-precision value in frs1 to double-precision, then write the result to frd
Definition
----------
Name : FCVT.D.S_V0
Mnemonic : FCVT.D.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+ff2 : No description ([funct5|funct2|rs2c |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.D.W (FCVT.D.W_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Word to Float (DP): Convert the 64-bit signed integer in rs1 to a double-precision value, then write the result to frd
Definition
----------
Name : FCVT.D.W_V0
Mnemonic : FCVT.D.W
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.D.WU (FCVT.D.WU_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Word Unsigned to Float (DP): Convert the 64-bit unsigned integer in rs1 to a double-precision value, then write the result to frd
Definition
----------
Name : FCVT.D.WU_V0
Mnemonic : FCVT.D.WU
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.L.D (FCVT.L.D_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Double Word (DP): Convert the double-precision value in frs1 to a 64-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.L.D_V0
Mnemonic : FCVT.L.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.L.D (FCVT.L.D_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Double Word (DP): Convert the double-precision value in frs1 to a 64-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.L.D_V1
Mnemonic : FCVT.L.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.L.S (FCVT.L.S_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Double Word (SP): Convert the single-precision value in frs1 to a 64-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.L.S_V0
Mnemonic : FCVT.L.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.L.S (FCVT.L.S_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Double Word (SP): Convert the single-precision value in frs1 to a 64-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.L.S_V1
Mnemonic : FCVT.L.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.LU.D (FCVT.LU.D_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Double Word Unsigned (DP): Convert the double-precision value in frs1 to a 64-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.LU.D_V0
Mnemonic : FCVT.LU.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.LU.D (FCVT.LU.D_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Double Word Unsigned (DP): Convert the double-precision value in frs1 to a 64-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.LU.D_V1
Mnemonic : FCVT.LU.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.LU.S (FCVT.LU.S_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Double Word Unsigned (SP): Convert the single-precision value in frs1 to a 64-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.LU.S_V0
Mnemonic : FCVT.LU.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.LU.S (FCVT.LU.S_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Double Word Unsigned (SP): Convert the single-precision value in frs1 to a 64-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.LU.S_V1
Mnemonic : FCVT.LU.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.D (FCVT.S.D_V0) OPC:0x 53 Format: r-m+ff2 Description: FP Convert DP to SP: Convert the double-precision value in frs1 to single-precision, then write the result to frd
Definition
----------
Name : FCVT.S.D_V0
Mnemonic : FCVT.S.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+ff2 : No description ([funct5|funct2|rs2c |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.D (FCVT.S.D_V1) OPC:0x 53 Format:r-m+ff2rm Description: FP Convert DP to SP: Convert the double-precision value in frs1 to single-precision, then write the result to frd
Definition
----------
Name : FCVT.S.D_V1
Mnemonic : FCVT.S.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+ff2rm : No description ([funct5|funct2|rs2c |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.L (FCVT.S.L_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Double Word to Float (SP): Convert the 64-bit signed integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.L_V0
Mnemonic : FCVT.S.L
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.L (FCVT.S.L_V1) OPC:0x 53 Format:r-m+fr2rm Description: FP Convert Double Word to Float (SP): Convert the 64-bit signed integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.L_V1
Mnemonic : FCVT.S.L
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2rm : No description ([funct5|funct2|rs2c | rs1 |rm| frd |opcode ])
Assembly : OPC frd, rs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.LU (FCVT.S.LU_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Double Word Unsigned to Float (SP): Convert the 64-bit unsigned integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.LU_V0
Mnemonic : FCVT.S.LU
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.LU (FCVT.S.LU_V1) OPC:0x 53 Format:r-m+fr2rm Description: FP Convert Double Word Unsigned to Float (SP): Convert the 64-bit unsigned integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.LU_V1
Mnemonic : FCVT.S.LU
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2rm : No description ([funct5|funct2|rs2c | rs1 |rm| frd |opcode ])
Assembly : OPC frd, rs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.W (FCVT.S.W_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Word to Float (SP): Convert the 32-bit signed integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.W_V0
Mnemonic : FCVT.S.W
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.W (FCVT.S.W_V1) OPC:0x 53 Format:r-m+fr2rm Description: FP Convert Word to Float (SP): Convert the 32-bit signed integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.W_V1
Mnemonic : FCVT.S.W
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2rm : No description ([funct5|funct2|rs2c | rs1 |rm| frd |opcode ])
Assembly : OPC frd, rs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.WU (FCVT.S.WU_V0) OPC:0x 53 Format: r-m+fr2 Description: FP Convert Word Unsigned to Float (SP): Convert the 32-bit unsigned integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.WU_V0
Mnemonic : FCVT.S.WU
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2 : No description ([funct5|funct2|rs2c | rs1 |rmns| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.S.WU (FCVT.S.WU_V1) OPC:0x 53 Format:r-m+fr2rm Description: FP Convert Word Unsigned to Float (SP): Convert the 32-bit unsigned integer in rs1 to a single-precision value, then write the result to frd
Definition
----------
Name : FCVT.S.WU_V1
Mnemonic : FCVT.S.WU
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+fr2rm : No description ([funct5|funct2|rs2c | rs1 |rm| frd |opcode ])
Assembly : OPC frd, rs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.W.D (FCVT.W.D_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Word (DP): Convert the double-precision value in frs1 to a 32-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.W.D_V0
Mnemonic : FCVT.W.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.W.D (FCVT.W.D_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Word (DP): Convert the double-precision value in frs1 to a 32-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.W.D_V1
Mnemonic : FCVT.W.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.W.S (FCVT.W.S_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Word (SP): Convert the single-precision value in frs1 to a 32-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.W.S_V0
Mnemonic : FCVT.W.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.W.S (FCVT.W.S_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Word (SP): Convert the single-precision value in frs1 to a 32-bit signed integer, then write the result to rd
Definition
----------
Name : FCVT.W.S_V1
Mnemonic : FCVT.W.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.WU.D (FCVT.WU.D_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Word Unsigned (DP): Convert the double-precision value in frs1 to a 32-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.WU.D_V0
Mnemonic : FCVT.WU.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.WU.D (FCVT.WU.D_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Word Unsigned (DP): Convert the double-precision value in frs1 to a 32-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.WU.D_V1
Mnemonic : FCVT.WU.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.WU.S (FCVT.WU.S_V0) OPC:0x 53 Format: r-m+rf2 Description: FP Convert Float to Word Unsigned (SP): Convert the single-precision value in frs1 to a 32-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.WU.S_V0
Mnemonic : FCVT.WU.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2 : No description ([funct5|funct2|rs2c |frs1 |rmns| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FCVT.WU.S (FCVT.WU.S_V1) OPC:0x 53 Format:r-m+rf2rm Description: FP Convert Float to Word Unsigned (SP): Convert the single-precision value in frs1 to a 32-bit unsigned integer, then write the result to rd
Definition
----------
Name : FCVT.WU.S_V1
Mnemonic : FCVT.WU.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+rf2rm : No description ([funct5|funct2|rs2c |frs1 |rm| rd |opcode ])
Assembly : OPC rd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FDIV.D ( FDIV.D_V0) OPC:0x 53 Format: r-m+3f Description: FP Divide (DP): Divide the double-precision value in frs1 into frs2, then write the result to frd
Definition
----------
Name : FDIV.D_V0
Mnemonic : FDIV.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FDIV.D ( FDIV.D_V1) OPC:0x 53 Format:r-m+3frm Description: FP Divide (DP): Divide the double-precision value in frs1 into frs2, then write the result to frd
Definition
----------
Name : FDIV.D_V1
Mnemonic : FDIV.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FDIV.S ( FDIV.S_V0) OPC:0x 53 Format: r-m+3f Description: FP Divide (SP): Divide the single-precision value in frs1 into frs2, then write the result to frd
Definition
----------
Name : FDIV.S_V0
Mnemonic : FDIV.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FDIV.S ( FDIV.S_V1) OPC:0x 53 Format:r-m+3frm Description: FP Divide (SP): Divide the single-precision value in frs1 into frs2, then write the result to frd
Definition
----------
Name : FDIV.S_V1
Mnemonic : FDIV.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FENCE.I (FENCE.I_V0) OPC:0x f Format: none Description: Fence Instruction: Synchronize the instruction and data streams
Definition
----------
Name : FENCE.I_V0
Mnemonic : FENCE.I
Opcode : f
Instr. Checks :
Target Checks :
Format
------
none : No description ([ none_imm12 |rs1c |funct3| rdc |opcode ])
Assembly : OPC
Fieldname : none_imm12 (bitsize: 12)
Fieldname : rs1c (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rdc (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FENCE ( FENCE_V0) OPC:0x f Format: r-f Description: Fence: Ordcer device I/O and memory accesses viewed by other threads and devices
Definition
----------
Name : FENCE_V0
Mnemonic : FENCE
Opcode : f
Operand pred : pred : 4-bit immediate (OperandImmRange) -- Input: True Output: False
Operand succ : succ : 4-bit immediate (OperandImmRange) -- Input: True Output: False
Instr. Checks :
Target Checks :
Format
------
r-f : No description ([imm4|pred|succ|rs1c |funct3| rdc |opcode ])
Assembly : OPC pred, succ
Fieldname : imm4 (bitsize: 4)
Fieldname : pred (bitsize: 4)
Fieldname : succ (bitsize: 4)
Fieldname : rs1c (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rdc (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FEQ.D ( FEQ.D_V0) OPC:0x 53 Format: r+rff Description: FP Equal (DP): Set rd to 1 if frs1 is equal to frs2, otherwise set rd to 0
Definition
----------
Name : FEQ.D_V0
Mnemonic : FEQ.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rff : No description ([funct5|funct2|frs2 |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FEQ.S ( FEQ.S_V0) OPC:0x 53 Format: r+rff Description: FP Equal (SP): Set rd to 1 if the single-precision value in frs1 is equal to frs2, otherwise set rd to 0
Definition
----------
Name : FEQ.S_V0
Mnemonic : FEQ.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rff : No description ([funct5|funct2|frs2 |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FLD ( FLD_V0) OPC:0x 7 Format: i+lf Description: FP Load (DP): Loads a double-precision foating-point value from memory into foating-point register frd
Definition
----------
Name : FLD_V0
Mnemonic : FLD
Opcode : 7
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+lf : No description ([ i_imm12 | rs1 |funct3| frd |opcode ])
Assembly : OPC frd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FLE.D ( FLE.D_V0) OPC:0x 53 Format: r+rff Description: FP Less Than Equal (DP): Set rd to 1 if frs1 is less than or equal to frs2, otherwise set rd to 0
Definition
----------
Name : FLE.D_V0
Mnemonic : FLE.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rff : No description ([funct5|funct2|frs2 |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FLE.S ( FLE.S_V0) OPC:0x 53 Format: r+rff Description: FP Less Than Equal (SP): Set rd to 1 if the single-precision value in frs1 is less than or equal to frs2, otherwise set rd to 0
Definition
----------
Name : FLE.S_V0
Mnemonic : FLE.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rff : No description ([funct5|funct2|frs2 |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FLT.D ( FLT.D_V0) OPC:0x 53 Format: r+rff Description: FP Less Than (DP): Set rd to 1 if frs1 is less than frs2, otherwise set rd to 0
Definition
----------
Name : FLT.D_V0
Mnemonic : FLT.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rff : No description ([funct5|funct2|frs2 |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FLT.S ( FLT.S_V0) OPC:0x 53 Format: r+rff Description: FP Less Than (SP): Set rd to 1 if the single-precision value in frs1 is less than frs2, otherwise set rd to 0
Definition
----------
Name : FLT.S_V0
Mnemonic : FLT.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rff : No description ([funct5|funct2|frs2 |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FLW ( FLW_V0) OPC:0x 7 Format: i+lf Description: FP Load (SP): Loads a single-precision foating-point value from memory into foating-point register frd
Definition
----------
Name : FLW_V0
Mnemonic : FLW
Opcode : 7
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+lf : No description ([ i_imm12 | rs1 |funct3| frd |opcode ])
Assembly : OPC frd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMADD.D (FMADD.D_V0) OPC:0x 43 Format: r4-m Description: FP Fused Multiply Add (DP): Multiply the double-precision values in frs1 and frs2, then add rs3 and write the result to frd
Definition
----------
Name : FMADD.D_V0
Mnemonic : FMADD.D
Opcode : 43
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMADD.D (FMADD.D_V1) OPC:0x 43 Format: r4-mrm Description: FP Fused Multiply Add (DP): Multiply the double-precision values in frs1 and frs2, then add rs3 and write the result to frd
Definition
----------
Name : FMADD.D_V1
Mnemonic : FMADD.D
Opcode : 43
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMADD.S (FMADD.S_V0) OPC:0x 43 Format: r4-m Description: FP Fused Multiply Add (SP): Multiply the single-precision values in frs1 and frs2, then add rs3 and write the result to frd
Definition
----------
Name : FMADD.S_V0
Mnemonic : FMADD.S
Opcode : 43
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMADD.S (FMADD.S_V1) OPC:0x 43 Format: r4-mrm Description: FP Fused Multiply Add (SP): Multiply the single-precision values in frs1 and frs2, then add rs3 and write the result to frd
Definition
----------
Name : FMADD.S_V1
Mnemonic : FMADD.S
Opcode : 43
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMAX.D ( FMAX.D_V0) OPC:0x 53 Format: r+3f Description: FP Maximum (DP)
Definition
----------
Name : FMAX.D_V0
Mnemonic : FMAX.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMAX.S ( FMAX.S_V0) OPC:0x 53 Format: r+3f Description: FP Maximum (SP): Take the larger single-precision value from frs1 and frs2, then write the result to frd: Take the larger double-precision value from frs1 and frs2, then write the result to frd: Take the larger quadruple-precision value from frs1 and frs2, then write the result to frd
Definition
----------
Name : FMAX.S_V0
Mnemonic : FMAX.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMIN.D ( FMIN.D_V0) OPC:0x 53 Format: r+3f Description: FP Minimum (DP)
Definition
----------
Name : FMIN.D_V0
Mnemonic : FMIN.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMIN.S ( FMIN.S_V0) OPC:0x 53 Format: r+3f Description: FP Minimum (SP): Take the smaller single-precision value from frs1 and frs2, then write the result to frd: Take the smaller double-precision value from frs1 and frs2, then write the result to frd: Take the smaller quadruple-precision value from frs1 and frs2, then write the result to frd
Definition
----------
Name : FMIN.S_V0
Mnemonic : FMIN.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMSUB.D (FMSUB.D_V0) OPC:0x 47 Format: r4-m Description: FP Fused Multiply Subtract (DP): Multiply the double-precision values in frs1 and frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FMSUB.D_V0
Mnemonic : FMSUB.D
Opcode : 47
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMSUB.D (FMSUB.D_V1) OPC:0x 47 Format: r4-mrm Description: FP Fused Multiply Subtract (DP): Multiply the double-precision values in frs1 and frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FMSUB.D_V1
Mnemonic : FMSUB.D
Opcode : 47
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMSUB.S (FMSUB.S_V0) OPC:0x 47 Format: r4-m Description: FP Fused Multiply Subtract (SP): Multiply the single-precision values in frs1 and frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FMSUB.S_V0
Mnemonic : FMSUB.S
Opcode : 47
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMSUB.S (FMSUB.S_V1) OPC:0x 47 Format: r4-mrm Description: FP Fused Multiply Subtract (SP): Multiply the single-precision values in frs1 and frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FMSUB.S_V1
Mnemonic : FMSUB.S
Opcode : 47
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMUL.D ( FMUL.D_V0) OPC:0x 53 Format: r-m+3f Description: FP Multiply (DP): Multiply the double-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FMUL.D_V0
Mnemonic : FMUL.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMUL.D ( FMUL.D_V1) OPC:0x 53 Format:r-m+3frm Description: FP Multiply (DP): Multiply the double-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FMUL.D_V1
Mnemonic : FMUL.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMUL.S ( FMUL.S_V0) OPC:0x 53 Format: r-m+3f Description: FP Multiply (SP): Multiply the single-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FMUL.S_V0
Mnemonic : FMUL.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMUL.S ( FMUL.S_V1) OPC:0x 53 Format:r-m+3frm Description: FP Multiply (SP): Multiply the single-precision values in frs1 and frs2, then write the result to frd
Definition
----------
Name : FMUL.S_V1
Mnemonic : FMUL.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMV.D.X (FMV.D.X_V0) OPC:0x 53 Format: r+fr2 Description: FP Move from Integer Register (DP): Write the 64-bit integer register rs1 into the double-precision register frd
Definition
----------
Name : FMV.D.X_V0
Mnemonic : FMV.D.X
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+fr2 : No description ([funct5|funct2|rs2c | rs1 |funct3| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMV.S.X (FMV.S.X_V0) OPC:0x 53 Format: r+fr2 Description: FP Move from Integer Register (SP): Write the lower 32-bits of the integer register rs1 into the single-precision register frd
Definition
----------
Name : FMV.S.X_V0
Mnemonic : FMV.S.X
Opcode : 53
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+fr2 : No description ([funct5|funct2|rs2c | rs1 |funct3| frd |opcode ])
Assembly : OPC frd, rs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMV.X.D (FMV.X.D_V0) OPC:0x 53 Format: r+rf2 Description: FP Move to Integer Register (DP): Write the sign extended double-precision value in frs1 into integer register rd
Definition
----------
Name : FMV.X.D_V0
Mnemonic : FMV.X.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rf2 : No description ([funct5|funct2|rs2c |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FMV.X.S (FMV.X.S_V0) OPC:0x 53 Format: r+rf2 Description: FP Move to Integer Register (SP): Write the sign extended single-precision value in frs1 into the integer register rd
Definition
----------
Name : FMV.X.S_V0
Mnemonic : FMV.X.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+rf2 : No description ([funct5|funct2|rs2c |frs1 |funct3| rd |opcode ])
Assembly : OPC rd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMADD.D (FNMADD.D_V0) OPC:0x 4f Format: r4-m Description: FP Negate fused Multiply Add (DP): Multiply the double-precision value in frs1 with the negated value in frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FNMADD.D_V0
Mnemonic : FNMADD.D
Opcode : 4f
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMADD.D (FNMADD.D_V1) OPC:0x 4f Format: r4-mrm Description: FP Negate fused Multiply Add (DP): Multiply the double-precision value in frs1 with the negated value in frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FNMADD.D_V1
Mnemonic : FNMADD.D
Opcode : 4f
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMADD.S (FNMADD.S_V0) OPC:0x 4f Format: r4-m Description: FP Negate fused Multiply Add (SP): Multiply the single-precision value in frs1 with the negated value in frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FNMADD.S_V0
Mnemonic : FNMADD.S
Opcode : 4f
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMADD.S (FNMADD.S_V1) OPC:0x 4f Format: r4-mrm Description: FP Negate fused Multiply Add (SP): Multiply the single-precision value in frs1 with the negated value in frs2, then subtract rs3 and write the result to frd
Definition
----------
Name : FNMADD.S_V1
Mnemonic : FNMADD.S
Opcode : 4f
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMSUB.D (FNMSUB.D_V0) OPC:0x 4b Format: r4-m Description: FP Negate fused Multiply Subtract (DP): Multiply the double-precision value in frs1 with the negated value in frs2, then add rs3 and write the result to frd
Definition
----------
Name : FNMSUB.D_V0
Mnemonic : FNMSUB.D
Opcode : 4b
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMSUB.D (FNMSUB.D_V1) OPC:0x 4b Format: r4-mrm Description: FP Negate fused Multiply Subtract (DP): Multiply the double-precision value in frs1 with the negated value in frs2, then add rs3 and write the result to frd
Definition
----------
Name : FNMSUB.D_V1
Mnemonic : FNMSUB.D
Opcode : 4b
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMSUB.S (FNMSUB.S_V0) OPC:0x 4b Format: r4-m Description: FP Negate fused Multiply Subtract (SP): Multiply the single-precision value in frs1 with the negated value in frs2, then add rs3 and write the result to frd
Definition
----------
Name : FNMSUB.S_V0
Mnemonic : FNMSUB.S
Opcode : 4b
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-m : No description ([frs3 |funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FNMSUB.S (FNMSUB.S_V1) OPC:0x 4b Format: r4-mrm Description: FP Negate fused Multiply Subtract (SP): Multiply the single-precision value in frs1 with the negated value in frs2, then add rs3 and write the result to frd
Definition
----------
Name : FNMSUB.S_V1
Mnemonic : FNMSUB.S
Opcode : 4b
Operand frs3 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r4-mrm : No description ([frs3 |funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, frs3, rm
Fieldname : frs3 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSD ( FSD_V0) OPC:0x 27 Format: s+f Description: FP Store (DP): Stores a double-precision foating-point value from foating-point register frs2 to memory
Definition
----------
Name : FSD_V0
Mnemonic : FSD
Opcode : 27
Operand s_imm7 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand s_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['s_imm7', 'rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
s+f : No description ([s_imm7 |frs2 | rs1 |funct3|s_imm5|opcode ])
Assembly : OPC frs2, s_imm12(rs1)
Fieldname : s_imm7 (bitsize: 7)
Fieldname : frs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : s_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSGNJ.D (FSGNJ.D_V0) OPC:0x 53 Format: r+3f Description: FP to Sign-injection (DP): Take the double-precision value from frs1 and inject the sign bit from frs2, then write the result to frd
Definition
----------
Name : FSGNJ.D_V0
Mnemonic : FSGNJ.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSGNJ.S (FSGNJ.S_V0) OPC:0x 53 Format: r+3f Description: FP Sign-injection (SP): Take the single-precision value from frs1 and inject the sign bit from frs2, then write the result to frd
Definition
----------
Name : FSGNJ.S_V0
Mnemonic : FSGNJ.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSGNJN.D (FSGNJN.D_V0) OPC:0x 53 Format: r+3f Description: FP to Sign-injection Negate (DP): Take the double-precision value from frs1 and inject the negated sign bit from frs2, then write the result to frd
Definition
----------
Name : FSGNJN.D_V0
Mnemonic : FSGNJN.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSGNJN.S (FSGNJN.S_V0) OPC:0x 53 Format: r+3f Description: FP Sign-injection Negate (SP): Take the single-precision value from frs1 and inject the negated sign bit from frs2, then write the result to frd
Definition
----------
Name : FSGNJN.S_V0
Mnemonic : FSGNJN.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSGNJX.D (FSGNJX.D_V0) OPC:0x 53 Format: r+3f Description: FP to Sign-injection Xor (DP): Take the double-precision value from frs1 and inject the xor of the sign bits frs1 and frs2, then write the result to frd
Definition
----------
Name : FSGNJX.D_V0
Mnemonic : FSGNJX.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSGNJX.S (FSGNJX.S_V0) OPC:0x 53 Format: r+3f Description: FP Sign-injection Xor (SP): Take the single-precision value from frs1 and inject the xor of the sign bits frs1 and frs2, then write the result to frd
Definition
----------
Name : FSGNJX.S_V0
Mnemonic : FSGNJX.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r+3f : No description ([funct5|funct2|frs2 |frs1 |funct3| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSQRT.D (FSQRT.D_V0) OPC:0x 53 Format: r-m+ff2 Description: Floating Square Root (DP): Calculate the square root of the double-precision value in frs1, then write the result to frd
Definition
----------
Name : FSQRT.D_V0
Mnemonic : FSQRT.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+ff2 : No description ([funct5|funct2|rs2c |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSQRT.D (FSQRT.D_V1) OPC:0x 53 Format:r-m+ff2rm Description: Floating Square Root (DP): Calculate the square root of the double-precision value in frs1, then write the result to frd
Definition
----------
Name : FSQRT.D_V1
Mnemonic : FSQRT.D
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+ff2rm : No description ([funct5|funct2|rs2c |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSQRT.S (FSQRT.S_V0) OPC:0x 53 Format: r-m+ff2 Description: FP Square Root (SP): Calculate the square root of the single-precision value in frs1, then write the result to frd
Definition
----------
Name : FSQRT.S_V0
Mnemonic : FSQRT.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+ff2 : No description ([funct5|funct2|rs2c |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSQRT.S (FSQRT.S_V1) OPC:0x 53 Format:r-m+ff2rm Description: FP Square Root (SP): Calculate the square root of the single-precision value in frs1, then write the result to frd
Definition
----------
Name : FSQRT.S_V1
Mnemonic : FSQRT.S
Opcode : 53
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+ff2rm : No description ([funct5|funct2|rs2c |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2c (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSUB.D ( FSUB.D_V0) OPC:0x 53 Format: r-m+3f Description: FP Subtract (DP): Subtract the double-precision values in frs1 from frs2, then write the result to frd
Definition
----------
Name : FSUB.D_V0
Mnemonic : FSUB.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSUB.D ( FSUB.D_V1) OPC:0x 53 Format:r-m+3frm Description: FP Subtract (DP): Subtract the double-precision values in frs1 from frs2, then write the result to frd
Definition
----------
Name : FSUB.D_V1
Mnemonic : FSUB.D
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSUB.S ( FSUB.S_V0) OPC:0x 53 Format: r-m+3f Description: FP Subtract (SP): Subtract the single-precision values in frs1 from frs2, then write the result to frd
Definition
----------
Name : FSUB.S_V0
Mnemonic : FSUB.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3f : No description ([funct5|funct2|frs2 |frs1 |rmns| frd |opcode ])
Assembly : OPC frd, frs1, frs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rmns (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSUB.S ( FSUB.S_V1) OPC:0x 53 Format:r-m+3frm Description: FP Subtract (SP): Subtract the single-precision values in frs1 from frs2, then write the result to frd
Definition
----------
Name : FSUB.S_V1
Mnemonic : FSUB.S
Opcode : 53
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand frs1 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rm : rm : 3-bit immediate for rounding mode (OperandValueSet) -- Input: False Output: False
Operand frd : freg : Floating Point Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r-m+3frm : No description ([funct5|funct2|frs2 |frs1 |rm| frd |opcode ])
Assembly : OPC frd, frs1, frs2, rm
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : frs2 (bitsize: 5)
Fieldname : frs1 (bitsize: 5)
Fieldname : rm (bitsize: 3)
Fieldname : frd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
FSW ( FSW_V0) OPC:0x 27 Format: s+f Description: FP Store (SP): Stores a single-precision foating-point value from foating-point register frs2 to memory
Definition
----------
Name : FSW_V0
Mnemonic : FSW
Opcode : 27
Operand s_imm7 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand frs2 : freg : Floating Point Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand s_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['s_imm7', 'rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
s+f : No description ([s_imm7 |frs2 | rs1 |funct3|s_imm5|opcode ])
Assembly : OPC frs2, s_imm12(rs1)
Fieldname : s_imm7 (bitsize: 7)
Fieldname : frs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : s_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
JAL ( JAL_V0) OPC:0x 6f Format: uj Description: Jump and Link: Jump to the PC plus 20-bit signed immediate while saving PC+4 into rd
Definition
----------
Name : JAL_V0
Mnemonic : JAL
Opcode : 6f
Operand uj_imm20 : @uj_imm20 : Relative displacement (bit size 20) (InstructionAddressRelativeOperand) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['uj_imm20']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
uj : No description ([ uj_imm20 | rd |opcode ])
Assembly : OPC rd, uj_imm20
Fieldname : uj_imm20 (bitsize: 20)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : True (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
JALR ( JALR_V0) OPC:0x 67 Format: i+o Description: Jump and Link Register: Jump to rs1 plus the 12-bit signed immediate while saving PC+4 into rd
Definition
----------
Name : JALR_V0
Mnemonic : JALR
Opcode : 67
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : False
Store : False
Prefetch : False
Address generator : False
Branch target : True
Instr. Checks :
Target Checks :
Format
------
i+o : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : True (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LB ( LB_V0) OPC:0x 3 Format: i+l Description: Load Byte: Load 8-bit value from addr in rs1 plus the 12-bit signed immediate and place sign-extended result into rd
Definition
----------
Name : LB_V0
Mnemonic : LB
Opcode : 3
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+l : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LBU ( LBU_V0) OPC:0x 3 Format: i+l Description: Load Byte Unsigned: Load 8-bit value from addr in rs1 plus the 12-bit signed immediate and place zero-extended result into rd
Definition
----------
Name : LBU_V0
Mnemonic : LBU
Opcode : 3
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+l : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LD ( LD_V0) OPC:0x 3 Format: i+l Description: Load Double: Load 64-bit value from addr in rs1 plus 12-bit signed immediate and place sign-extended result into rd
Definition
----------
Name : LD_V0
Mnemonic : LD
Opcode : 3
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+l : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LH ( LH_V0) OPC:0x 3 Format: i+l Description: Load Half: Load 16-bit value from addr in rs1 plus the 12-bit signed immediate and place sign-extended result into rd
Definition
----------
Name : LH_V0
Mnemonic : LH
Opcode : 3
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+l : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LHU ( LHU_V0) OPC:0x 3 Format: i+l Description: Load Half Unsigned: Load 32-bit value from addr in rs1 plus the 12-bit signed immediate and place zero-extended result into rd
Definition
----------
Name : LHU_V0
Mnemonic : LHU
Opcode : 3
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+l : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LR.D ( LR.D_V0) OPC:0x 2f Format: r-l2 Description: Load Reserved Double Word: Load double word from address in rs1, place the sign-extended result in rd and register a reservation on the memory word
Definition
----------
Name : LR.D_V0
Mnemonic : LR.D
Opcode : 2f
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-l2 : No description ([funct5|aq|rl|rs2c | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LR.W ( LR.W_V0) OPC:0x 2f Format: r-l2 Description: Load Reserved Word: Load word from address in rs1, place the sign-extended result in rd and register a reservation on the memory word
Definition
----------
Name : LR.W_V0
Mnemonic : LR.W
Opcode : 2f
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-l2 : No description ([funct5|aq|rl|rs2c | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2c (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LUI ( LUI_V0) OPC:0x 37 Format: u Description: Load Upper Immediate: Set and sign extend the 20-bit immediate (shited 12 bits left) and zero the bottom 12 bits into rd
Definition
----------
Name : LUI_V0
Mnemonic : LUI
Opcode : 37
Operand u_imm20 : u.imm20 : 20-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
u : No description ([ u_imm20 | rd |opcode ])
Assembly : OPC rd, u_imm20
Fieldname : u_imm20 (bitsize: 20)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LW ( LW_V0) OPC:0x 3 Format: i+l Description: Load Word: Load 32-bit value from addr in rs1 plus the 12-bit signed immediate and place sign-extended result into rd
Definition
----------
Name : LW_V0
Mnemonic : LW
Opcode : 3
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+l : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
LWU ( LWU_V0) OPC:0x 3 Format: i+l Description: Load Word Unsigned: Load 32-bit value from addr in rs1 plus the 12-bit signed immediate and place zero-extended result into rd
Definition
----------
Name : LWU_V0
Mnemonic : LWU
Opcode : 3
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['i_imm12', 'rs1']
Length : ['no_field_0']
Load : True
Store : False
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
i+l : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, i_imm12(rs1)
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
MUL ( MUL_V0) OPC:0x 33 Format: r Description: Multiply: Multiply rs1 by rs2 and place the result in rd
Definition
----------
Name : MUL_V0
Mnemonic : MUL
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
MULH ( MULH_V0) OPC:0x 33 Format: r Description: Multiply High Signed Signed: Multiply signed rs1 by signed rs2 and place the high bits of the result in rd
Definition
----------
Name : MULH_V0
Mnemonic : MULH
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
MULHSU ( MULHSU_V0) OPC:0x 33 Format: r Description: Multiply High Signed Unsigned: Multiply signed rs1 by unsigned rs2 and place the high bits of the result in rd
Definition
----------
Name : MULHSU_V0
Mnemonic : MULHSU
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
MULHU ( MULHU_V0) OPC:0x 33 Format: r Description: Multiply High Unsigned Unsigned: Multiply unsigned rs1 by unsigned rs2 and place the high bits of the result in rd
Definition
----------
Name : MULHU_V0
Mnemonic : MULHU
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
MULW ( MULW_V0) OPC:0x 3b Format: r Description: Multiple Word: Multiply with lower 32-bits of rs1 by the lower 32-bits of rs2 and place the result in rd
Definition
----------
Name : MULW_V0
Mnemonic : MULW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
OR ( OR_V0) OPC:0x 33 Format: r Description: Or: Set rd to the bitwise or of rs1 and rs2
Definition
----------
Name : OR_V0
Mnemonic : OR
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
ORI ( ORI_V0) OPC:0x 13 Format: i Description: Or Immediate: Set rd to the bitwise or of rs1 with the sign-extended 12-bit immediate
Definition
----------
Name : ORI_V0
Mnemonic : ORI
Opcode : 13
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_imm12
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
REM ( REM_V0) OPC:0x 33 Format: r Description: Remainder Signed: Divide rs1 (dividend) by rs2 (divisor) and place the remainder in rd (signed)
Definition
----------
Name : REM_V0
Mnemonic : REM
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
REMU ( REMU_V0) OPC:0x 33 Format: r Description: Remainder Unsigned: Divide rs1 (dividend) by rs2 (divisor) and place the remainder in rd (unsigned)
Definition
----------
Name : REMU_V0
Mnemonic : REMU
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
REMUW ( REMUW_V0) OPC:0x 3b Format: r Description: Remainder Unsigned Word: Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the remainder in rd (unsigned)
Definition
----------
Name : REMUW_V0
Mnemonic : REMUW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
REMW ( REMW_V0) OPC:0x 3b Format: r Description: Remainder Signed Word: Divide lower 32-bits of rs1 (dividend) by lower 32-bits of rs2 (divisor) and place the remainder in rd (signed)
Definition
----------
Name : REMW_V0
Mnemonic : REMW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SB ( SB_V0) OPC:0x 23 Format: s Description: Store Byte: Store 8-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate
Definition
----------
Name : SB_V0
Mnemonic : SB
Opcode : 23
Operand s_imm7 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand s_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['s_imm7', 'rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
s : No description ([s_imm7 | rs2 | rs1 |funct3|s_imm5|opcode ])
Assembly : OPC rs2, s_imm12(rs1)
Fieldname : s_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : s_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SC.D ( SC.D_V0) OPC:0x 2f Format: r-a Description: Store Conditional Double Word: Write double word in rs1 to the address in rs2 if a valid reservation exists, write 0 on success or 1 on failure to rd
Definition
----------
Name : SC.D_V0
Mnemonic : SC.D
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SC.W ( SC.W_V0) OPC:0x 2f Format: r-a Description: Store Conditional Word: Write word in rs1 to the address in rs2 if a valid reservation exists, write 0 on success or 1 on failure to rd
Definition
----------
Name : SC.W_V0
Mnemonic : SC.W
Opcode : 2f
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Memory Operand 0 :
Address : ['rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
r-a : No description ([funct5|aq|rl| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs2, (rs1)
Fieldname : funct5 (bitsize: 5)
Fieldname : aq (bitsize: 1)
Fieldname : rl (bitsize: 1)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SD ( SD_V0) OPC:0x 23 Format: s Description: Store Double: Store 64-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate
Definition
----------
Name : SD_V0
Mnemonic : SD
Opcode : 23
Operand s_imm7 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand s_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['s_imm7', 'rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
s : No description ([s_imm7 | rs2 | rs1 |funct3|s_imm5|opcode ])
Assembly : OPC rs2, s_imm12(rs1)
Fieldname : s_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : s_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SH ( SH_V0) OPC:0x 23 Format: s Description: Store Half: Store 16-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate
Definition
----------
Name : SH_V0
Mnemonic : SH
Opcode : 23
Operand s_imm7 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand s_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['s_imm7', 'rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
s : No description ([s_imm7 | rs2 | rs1 |funct3|s_imm5|opcode ])
Assembly : OPC rs2, s_imm12(rs1)
Fieldname : s_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : s_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLL ( SLL_V0) OPC:0x 33 Format: r Description: Shift Left Logical: Shift rs1 left by the by the lower 5 or 6 (RV32/64) bits in rs2 and place the result into rd
Definition
----------
Name : SLL_V0
Mnemonic : SLL
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLLI ( SLLI_V0) OPC:0x 13 Format: i-sh6 Description: Shift Left Logical Immediate: Shift rs1 left by the 5 or 6 (RV32/64) bit (RV64) immediate and place the result into rd
Definition
----------
Name : SLLI_V0
Mnemonic : SLLI
Opcode : 13
Operand i_shamt6 : u.imm6 : 6-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i-sh6 : No description ([i_imm6|i_shamt6| rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_shamt6
Fieldname : i_imm6 (bitsize: 6)
Fieldname : i_shamt6 (bitsize: 6)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLLIW ( SLLIW_V0) OPC:0x 1b Format: i-sh5 Description: Shift Left Logical Immediate Word: Shift 32-bit value in rs1 left by the 5 bit immediate and place the result into rd while zeroing upper bits
Definition
----------
Name : SLLIW_V0
Mnemonic : SLLIW
Opcode : 1b
Operand i_shamt5 : u.imm5 : 5-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i-sh5 : No description ([i_imm7 |i_shamt5| rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_shamt5
Fieldname : i_imm7 (bitsize: 7)
Fieldname : i_shamt5 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLLW ( SLLW_V0) OPC:0x 3b Format: r Description: Shift Left Logical Word: Shift 32-bit value in rs1 left by the by the lower 5 bits in rs2 and place the 32-bit result into rd
Definition
----------
Name : SLLW_V0
Mnemonic : SLLW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLT ( SLT_V0) OPC:0x 33 Format: r Description: Set Less Than: Set rd to 1 if rs1 is less than rs2, otherwise set rd to 0 (signed)
Definition
----------
Name : SLT_V0
Mnemonic : SLT
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLTI ( SLTI_V0) OPC:0x 13 Format: i Description: Set Less Than Immediate: Set rd to 1 if rs1 is less than the sign-extended 12-bit immediate, otherwise set rd to 0 (signed)
Definition
----------
Name : SLTI_V0
Mnemonic : SLTI
Opcode : 13
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_imm12
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLTIU ( SLTIU_V0) OPC:0x 13 Format: i Description: Set Less Than Immediate Unsigned: Set rd to 1 if rs1 is less than the sign-extended 12-bit immediate, otherwise set rd to 0 (unsigned)
Definition
----------
Name : SLTIU_V0
Mnemonic : SLTIU
Opcode : 13
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_imm12
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SLTU ( SLTU_V0) OPC:0x 33 Format: r Description: Set Less Than Unsigned: Set rd to 1 if rs1 is less than rs2, otherwise set rd to 0 (unsigned)
Definition
----------
Name : SLTU_V0
Mnemonic : SLTU
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRA ( SRA_V0) OPC:0x 33 Format: r Description: Shift Right Arithmetic: Shift rs1 right by the by the lower 5 or 6 (RV32/64) bits in rs2 and place the result into rd while retaining the sign
Definition
----------
Name : SRA_V0
Mnemonic : SRA
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRAI ( SRAI_V0) OPC:0x 13 Format: i-sh6 Description: Shift Right Arithmetic Immediate: Shift rs1 right by the 5 or 6 (RV32/64) bit immediate and place the result into rd while retaining the sign
Definition
----------
Name : SRAI_V0
Mnemonic : SRAI
Opcode : 13
Operand i_shamt6 : u.imm6 : 6-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i-sh6 : No description ([i_imm6|i_shamt6| rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_shamt6
Fieldname : i_imm6 (bitsize: 6)
Fieldname : i_shamt6 (bitsize: 6)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRAIW ( SRAIW_V0) OPC:0x 1b Format: i-sh5 Description: Shift Right Arithmetic Immediate Word: Shift 32-bit value in rs1 right by the 5 bit immediate and place the result into rd and retaining the sign
Definition
----------
Name : SRAIW_V0
Mnemonic : SRAIW
Opcode : 1b
Operand i_shamt5 : u.imm5 : 5-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i-sh5 : No description ([i_imm7 |i_shamt5| rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_shamt5
Fieldname : i_imm7 (bitsize: 7)
Fieldname : i_shamt5 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRAW ( SRAW_V0) OPC:0x 3b Format: r Description: Shift Right Arithmetic Word: Shift 32-bit value in rs1 right by the by the lower 5 bits in rs2 and place the 32-bit result into rd while retaining the sign
Definition
----------
Name : SRAW_V0
Mnemonic : SRAW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRL ( SRL_V0) OPC:0x 33 Format: r Description: Shift Right Logical: Shift rs1 right by the by the lower 5 or 6 (RV32/64) bits in rs2 and place the result into rd
Definition
----------
Name : SRL_V0
Mnemonic : SRL
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRLI ( SRLI_V0) OPC:0x 13 Format: i-sh6 Description: Shift Right Logical Immediate: Shift rs1 right by the 5 or 6 (RV32/64) bit immediate and place the result into rd
Definition
----------
Name : SRLI_V0
Mnemonic : SRLI
Opcode : 13
Operand i_shamt6 : u.imm6 : 6-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i-sh6 : No description ([i_imm6|i_shamt6| rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_shamt6
Fieldname : i_imm6 (bitsize: 6)
Fieldname : i_shamt6 (bitsize: 6)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRLIW ( SRLIW_V0) OPC:0x 1b Format: i-sh5 Description: Shift Right Logical Immediate Word: Shift 32-bit value in rs1 right by the 5 bit immediate and place the result into rd while zeroing upper bits
Definition
----------
Name : SRLIW_V0
Mnemonic : SRLIW
Opcode : 1b
Operand i_shamt5 : u.imm5 : 5-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i-sh5 : No description ([i_imm7 |i_shamt5| rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_shamt5
Fieldname : i_imm7 (bitsize: 7)
Fieldname : i_shamt5 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SRLW ( SRLW_V0) OPC:0x 3b Format: r Description: Shift Right Logical Word: Shift 32-bit value in rs1 right by the by the lower 5 bits in rs2 and place the 32-bit result into rd
Definition
----------
Name : SRLW_V0
Mnemonic : SRLW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SUB ( SUB_V0) OPC:0x 33 Format: r Description: Subtract: Subtract rs2 from rs1 and place the result into rd
Definition
----------
Name : SUB_V0
Mnemonic : SUB
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SUBW ( SUBW_V0) OPC:0x 3b Format: r Description: Subtract Word: Subtract 32-bit value in rs2 from rs1 and place the 32-bit result into rd
Definition
----------
Name : SUBW_V0
Mnemonic : SUBW
Opcode : 3b
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
SW ( SW_V0) OPC:0x 23 Format: s Description: Store Word: Store 32-bit value from the low bits of rs2 to addr in rs1 plus the 12-bit signed immediate
Definition
----------
Name : SW_V0
Mnemonic : SW
Opcode : 23
Operand s_imm7 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : rega : Integer Register (address base) (OperandReg) -- Input: True Output: False
Operand s_imm5 : Zero : Zero operand (special, not shown) (OperandConst) -- Input: True Output: False
Memory Operand 0 :
Address : ['s_imm7', 'rs1']
Length : ['no_field_0']
Load : False
Store : True
Prefetch : False
Address generator : False
Branch target : False
Instr. Checks :
Target Checks :
Format
------
s : No description ([s_imm7 | rs2 | rs1 |funct3|s_imm5|opcode ])
Assembly : OPC rs2, s_imm12(rs1)
Fieldname : s_imm7 (bitsize: 7)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : s_imm5 (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : True (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
XOR ( XOR_V0) OPC:0x 33 Format: r Description: Xor: Set rd to the bitwise xor of rs1 and rs2
Definition
----------
Name : XOR_V0
Mnemonic : XOR
Opcode : 33
Operand rs2 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
r : No description ([funct5|funct2| rs2 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, rs2
Fieldname : funct5 (bitsize: 5)
Fieldname : funct2 (bitsize: 2)
Fieldname : rs2 (bitsize: 5)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
XORI ( XORI_V0) OPC:0x 13 Format: i Description: Xor Immediate: Set rd to the bitwise xor of rs1 with the sign-extended 12-bit immediate
Definition
----------
Name : XORI_V0
Mnemonic : XORI
Opcode : 13
Operand i_imm12 : s.imm12 : signed 12-bit immediate (OperandImmRange) -- Input: True Output: False
Operand rs1 : reg : Integer Registers (OperandReg) -- Input: True Output: False
Operand rd : reg : Integer Registers (OperandReg) -- Input: False Output: True
Instr. Checks :
Target Checks :
Format
------
i : No description ([ i_imm12 | rs1 |funct3| rd |opcode ])
Assembly : OPC rd, rs1, i_imm12
Fieldname : i_imm12 (bitsize: 12)
Fieldname : rs1 (bitsize: 5)
Fieldname : funct3 (bitsize: 3)
Fieldname : rd (bitsize: 5)
Fieldname : opcode (bitsize: 7)
Property List
-------------
access_storage : False (Boolean indicating if the instruction has storage operands )
access_storage_with_update : False (Boolean indicating if the instruction accesses to storage and updates the source register with the generated address)
branch : False (Boolean indicating if the instruction is a branch )
branch_conditional : False (Boolean indicating if the instruction is a branch confitional )
branch_relative : False (Boolean indicating if the instruction is a relative branch )
decimal : False (Boolean indication if the instruction requires inputs in decimal format )
disable_asm : False (Boolean indicating if ASM generation is disabled for the instruction. If so, binary codification is used )
priviledged : False (Boolean indicating if the instruction is privileged )
switching : None (Input values required to maximize the computational switching )
unsupported : False (Boolean indicating if the instruction is unsupported )
Instructions defined: 189
Variants defined: 222
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Microarchitecture Name: riscv_generic
Microarchitecture Description: riscv_generic
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Element Types:
RISCVMicroarchitectureElementType('Core','Computing core')
RISCVMicroarchitectureElementType('DummyCache','DummyCache used when the cache hierarchy is not fully defined')
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Elements:
RISCVMicroarchitectureElement('Core','Core','Computing core')
RISCVMicroarchitectureElement('Cache','Cache_Core','DummyCache used when the cache hierarchy is not fully defined')
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Environment 'riscv64_linux_gcc': RISC-V architecture (64bit addressing mode), Linux operating system, GCC compiler